AnalogGym

⚠️ Important Notice on ngspice Version

The latest version of ngspice currently available through Conda (conda install -c conda-forge ngspice) is ngspice-41. However, this version has known limitations and may yield inaccurate simulation results, especially in DC sweeps involving temperature or current sources.

⚠️ We strongly recommend NOT using the Conda-provided ngspice.

Instead, please manually upgrade to ngspice-42 or later to ensure simulation correctness. These versions fix critical issues present in ngspice-41.

You can download newer releases from the official ngspice SourceForge repository.

🔧 Manual Upgrade Instructions

# Navigate to the bin directory of your Conda environment (example for Windows)
cd /Anaconda/envs/analoggym-env/Library/bin
# Replace the existing ngspice executable with the newer version you downloaded

About AnalogGym

This repository is the analog circuit synthesis testing suite, AnalogGym.

AnalogGym encompasses 30 circuit topologies in five key categories: sensing front ends, voltage references, AMPs, low dropout regulators (LDOs), and phase-locked loops (PLLs). Among these, the LDOs and AMPs support the open-source Ngspice simulator and the SkyWater  process design kit (PDK), allowing for greater accessibility and reproducibility.

Table of Contents

• Getting Started
• AnalogGym Contents
• Usage
  • Workflow in AnalogGym
  • Testbench
  • Simulation
  • Performance Extraction
  • Additional Resources
• Citation
• Contact

Getting Started

Examples of using the AnalogGym with the relational graph neural network and reinforcement learning algorithm¹, referencing this repository. A Docker version and a downloadable code package that can be run locally are provided.

AnalogGym Contents

The test circuits provided in AnalogGym include:

• netlist folder: Contains pre-packaged circuit files that require no modification.
• testbench folder: Includes testbench files for running simulations with the simulator.
• design variables folder: Stores the input parameters for each circuit separately.
• schematic folder: Provides circuit diagrams for reference and visualization.

Usage

Note that in the sky130 PDK, transistors have a drain-source breakdown voltage of 1.8V and a threshold voltage of 1V. Consequently, the supply voltage is maintained at 1.8V, rather than being reduced to 1.2V, to meet the required reliability and operational standards.

Workflow in AnalogGym

The design flow decouples circuit configuration from the optimization process, allowing for flexible parameter tuning. The circuit parameters are maintained in independent configuration files in the design variables folder. Different netlists can be switched in the testbench, with each netlist representing an encapsulated circuit.

Testbench

Line	Ngspice Testbench Description
1	.include ./path_to_spice_netlist/circuit_name — Include the SPICE netlist
2	.include ./path_to_decision_variable/circuit_name — Include the circuit parameters (decision variables)
3	.include ./mosfet_model/sky130_pdk/libs.tech/ngspice/corners/tt.spice — Include PDK, modify Process in PVT
4	.PARAM supply_voltage = 1.3 — Specify supply voltage for PVT
5	.temp 27 — Specify temperature for PVT
6	.PARAM PARAM_CLOAD = 10p — Specify load capacitance
…	Simulation commands; no modifications required.

Simulation

For the simulation setup and execution, you can check the following scripts:

• For the Amplifier simulation, refer to main_AMP.py.
• For the LDO simulation, refer to main_LDO.py.

Performance Extraction

When extracting performance metrics for the included AMP and LDO circuits, the following points should be noted:

• Amplifier (AMP):
  • For AMPs, Slew Rate (SR) and Settling Time are not directly measurable from simulations and must be derived from transient response analysis.
• Low-Dropout Regulator (LDO):
  • LDO performance varies under light load (5mA) and heavy load (55mA) conditions, as load current affects efficiency, stability, and response time. Light load (minload) may reduce power consumption but can slow response, while heavy load (maxload) demands a higher current supply while maintaining stable output voltage.

Two performance extraction scripts are provided for reference: AMP and LDO.

Additional Resources

• For a detailed tutorial on using Ngspice, please refer to this link.
• Detailed documentation can be found in doc, and our paper can be found here.

📌 Update Note: Adjustment to the $\mathrm{FOM}_{\text{AMP}}$ Formula Structure

✅ Original Formula

The originally defined amplifier $FOM_{AMP}$ is given as:

The last term represents a penalty factor, applied to suppress degradation in these ** metrics**: output noise voltage ($v_n$), temperature coefficient (TC), and input offset voltage ($v_{\mathrm{os}}$). Since these metrics are “smaller is better”, a penalty is applied when they exceed their respective reference values.

---

❌ Problem with the Original Expression

While the original expression intends to penalize only when degradation occurs (i.e., when a metric exceeds its reference), it presents a critical issue in implementation:

• If any metric is better than its reference, the corresponding indicator function $\mathbb{I}(\cdot)$ returns 0. This causes the entire product to become 0, making the denominator undefined or divergent.

🔁 Revised Expression

To address these issues, we reformulate the penalty term as:

This structure is logically equivalent to the original one: it penalizes only when a parameter exceeds its reference.

The updated $\mathrm{FOM}_{\text{AMP}}$ is:

Citation

Please cite us if you find AnalogGym useful.

• AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis, Jintao Li, Haochang Zhi, Ruiyu Lyu, Wangzhen Li, Zhaori Bi^*, Keren Zhu^*, Yanhan Zhen, Weiwei Shan, Changhao Yan, Fan Yang, Yun Li^*, and Xuan Zeng^* IEEE/ACM International Conference on Computer-Aided Design (ICCAD ‘24), October 27–31, 2024, New York, NY, USA

  @inproceedings{10.1145/3676536.3697117,
  author = {Li, Jintao and Zhi, Haochang and Lyu, Ruiyu and Li, Wangzhen and Bi, Zhaori and Zhu, Keren and Zeng, Yanhan and Shan, Weiwei and Yan, Changhao and Yang, Fan and Li, Yun and Zeng, Xuan},
  title = {AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis},
  year = {2025},
  isbn = {9798400710773},
  publisher = {Association for Computing Machinery},
  address = {New York, NY, USA},
  url = {https://doi.org/10.1145/3676536.3697117 },
  doi = {10.1145/3676536.3697117},
  booktitle = {Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design},
  articleno = {59},
  numpages = {9},
  keywords = {analog circuit optimization, electronic design automation},
  location = {Newark Liberty International Airport Marriott, New York, NY, USA},
  series = {ICCAD '24}
  }
  

Contact

If you have any questions, are seeking collaboration, or would like to contribute circuit designs, please get in touch with us at j.t.li@i4ai.org.

1. Z. Li and A. C. Carusone, “Design and Optimization of Low-Dropout Voltage Regulator Using Relational Graph Neural Network and Reinforcement Learning in Open-Source SKY130 Process,” 2023 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Francisco, CA, USA, 2023, pp. 01-09, doi: 10.1109/ICCAD57390.2023.10323720. ↩

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